1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly to a circuit structure including a semiconductor-based integrated circuit coupled to a passive element formed within a grid-array packaging substrate, and a method for forming such a structure.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
A proliferation in the use of devices employing wireless communication, such as wireless telephones, pagers, and personal digital assistants, has led to increased demands on the integrated circuit (IC) technology used in these devices. Many wireless applications involve the use of mixed mode IC""s, or circuits which process both analog and digital signals. For example, digital circuitry may be used for data processing functions in a device such as a wireless telephone, while analog circuitry may be used for transmission and/or reception of data over the wireless link. Differences between properties of analog and digital IC""s can make mixed mode circuit design and fabrication challenging. As an example, digital IC""s fabricated using silicon metal-oxide-semiconductor (MOS) technology typically operate at low power, and most of the circuit components, including logic gates, memory cells, and loads, may be formed using combinations or modifications of MOS transistors. By contrast, analog circuitry used in a transmitter may need to operate at a relatively high power in order to deliver sufficient signal power to the transmitting antenna. Furthermnore, the tuning and filtering circuitry typically used for wireless transmission and reception generally involves the use of passive circuit elements such as inductors and capacitors.
Formation of inductors in IC technology may be particularly challenging. In order for a tuning circuit or filter to efficiently select a desired frequency, an inductor used in the circuit should have a high xe2x80x9cquality factorxe2x80x9d Q. The quality factor of an element is proportional to the energy stored in the element divided by the energy dissipated or lost in the element per unit time. One way of achieving a high-Q inductor is therefore to minimize energy loss in the inductor. One mechanism of loss in an inductor is resistive heating, which is proportional to the resistance of the inductor. Another way in which energy may be lost from an inductor is by interaction of the electromagnetic field produced when power is applied to the inductor with a lossy medium proximate to the inductor. A lossy medium as used herein has a sufficient concentration of free charge carriers that interaction with an electromagnetic field can cause ohmic losses in the medium. Semiconductors are therefore generally lossy compared to insulators, and a semiconductor such as silicon is lossy compared to a semiconductor having a larger energy gap, such as gallium arsenide.
The loss mechanisms described above can contribute to difficulties in forming a high-Q inductor within a silicon-based IC. One approach to forming an inductor in an IC is to pattern a trace having a spiral geometry within a deposited conductive layer. The resistance of such an inductor is inversely proportional to the cross-sectional area of the patterned trace, which is in turn proportional to the thickness of the conductive layer. A thick conductive layer would therefore be desirable for forming a low-resistance inductor. Use of a conductor having low resistivity would also help to lower the resistance of the inductor. Low resistance is desirable for reducing the above-described resistive losses within the inductor.
However, the thickness of a conductive layer used in IC fabrication is generally limited because of the narrow interconnect feature sizes used in these circuits. For circuits having interconnect feature sizes of 0.25 micron or less, for example, interconnect metal thicknesses may be limited to approximately one micron or less. Thicker conductor layers for these narrow interconnect features could result in difficulty in filling the spaces between patterned interconnects with a dielectric, because deposition into high-aspect-ratio trenches can result in incomplete filling and/or void formation. This metal thickness limitation may be particularly applicable to the case for which copper is used as the interconnect metal. Copper has the lowest resistivity of the interconnect metals in current use, but copper interconnect formation is typically somewhat more involved than formation of interconnects from other metals such as aluminum. Copper interconnects may be formed by a damascene process, in which trenches are formed in a dielectric layer and metal is then deposited to fill the trenches, with excess metal subsequently removed, generally by chemical-mechanical polishing (CMP). A diffusion barrier/adhesion layer is generally deposited within the trenches, followed by a copper seed layer, and then a copper fill layer. The complexity of the copper interconnect formation process may particularly limit the aspect ratio of the trenches and thereby the thickness of the copper traces.
Because a spiral inductor formed within a silicon-based IC as described above would generally be formed in a layer of the circuit which also included interconnect lines for the circuit, the thickness of the inductor trace would be limited to that of the interconnect lines, though the feature size of the inductor trace may not be as small as that for the interconnect lines. Even in a case for which only the inductor were formed on a particular level of the IC, however, the thickness of the inductor metal would be limited by the amount of elevational disparity which can be accommodated by the planarization processes (typically CMP) used in fabricating the circuit.
In addition to the above-described ohmic losses within the inductor resulting from a nonzero resistance of the inductor metal trace, energy in an inductor formed within a silicon-based IC may also be lost through coupling of the inductor""s electromagnetic field with the nearby silicon substrate. An inductor formed within a metallization layer of an IC is generally displaced by no more than a few microns from the semiconductor substrate of the IC. The degree of electromagnetic coupling between the field of the inductor and the semiconductor can therefore be substantial. Interaction of the field of the inductor with silicon, which is relatively lossy compared to materials typically used for substrates in high-frequency circuits, may result in conduction in the silicon and thereby loss of energy from the inductor. The proximity of the silicon substrate may therefore also contribute to difficulty in forming a high-Q inductor in a silicon-based IC.
As an alternative to forming a spiral inductor as described above, inductors have also been formed on IC""s using wire-bonding wire. This wire has lower resistance than metallization traces, and coupling to the substrate is reduced because such an inductor extends above the surface of the IC and is therefore largely surrounded by air. Because wire-bonding equipment is not designed to produce coils of wire, however, the resulting inductors are generally short loops having relatively low inductance. Furthermore, the reproducibility of the inductor formation is limited, and hand xe2x80x9ctweakingxe2x80x9d of the inductor may be needed to adjust its inductance value.
Another approach to formation of circuits having high-Q inductors is hybrid circuit fabrication. Hybrid circuit fabrication typically involves mounting IC""s and discrete components onto a low-loss substrate, such as a ceramic substrate, and forming interconnections between these elements. In this way, a high-Q discrete inductor may be combined with a silicon-based IC. However, hybrid circuit fabrication requires additional assembly as compared to IC fabrication, and may be more expensive than IC fabrication when large quantities are produced. Hybrid circuits may also be considerably larger than IC""s performing similar functions, which can be disadvantageous for the manufacture of small, lightweight wireless communication devices.
It would therefore be desirable to develop a circuit structure in which a high-Q inductor or other passive circuit element may be combined with a semiconductor-based IC, and a method for forming such a circuit structure. Formation of inductors having a wide range of reproducible inductance values should be achievable by the method, and such inductors should have high quality factor. Furthermore, the circuit structure and its formation should be compatible with IC processing and packaging techniques.
The problems outlined above are in large part addressed by a circuit structure which includes a passive circuit element formed within a grid-array substrate as may be used for packaging of integrated circuits. The passive element may be formed using one or more conductive layers within the grid-array substrate. Contact pads formed within a semiconductor-based IC may be coupled to terminals of the passive circuit element, thereby forming a circuit including the passive element. The same grid-array substrate in which the passive element is formed is preferably also used for packaging of the IC, so that additional fabrication or assembly beyond that which would typically be employed in packaging the circuit is not required.
A grid-array substrate forms a part of a grid-array IC package having terminals for connection to a circuit board arranged as an array across a surface of the package. For mounting to an upper surface of a circuit board, for example, the terminals are arranged across a lower surface of the package. Forms which the terminals may take include pins, as in a pin-grid-array (PGA) package, or pads to which solder balls or bumps are attached, as in a ball-grid-array (BGA) package. The grid-array substrate forms the base of the grid-array package, and the terminals for connection to the circuit board are typically formed on one surface of the substrate, while pads for connection to the IC are formed on the opposite surface, or IC-mounting surface. The package may further include a cover and/or encapsulation layer for protection of the mounted IC. A grid array substrate is typically formed from materials similar to those used in forming circuit boards, having one or more insulating layers made from materials such as resins, polymers and/or ceramic materials and one or more conductive layers made from materials such as tungsten or copper.
Thicknesses of conductive layers within a grid-array substrate are typically several microns, e.g. 15 microns or more. A metal trace formed by patterning such a conductive layer may therefore have a much lower resistance than a similar trace formed in an interconnect metallization layer of an IC. Passive circuit elements formed using one or more conductive layers of a grid-array substrate, as included in the circuit structures described herein, may therefore have much lower resistance, and correspondingly reduced resistive energy losses, than similar circuit elements formed within a semiconductor-based IC. Such reduced energy losses are believed to allow formation of high-Q passive circuit elements such as inductors and capacitors. The quality factors of such passive circuit elements may further be improved by formation of the circuit elements within the grid-array substrate rather than within the semiconductor-based IC. Although the IC is mounted in close proximity to the grid-array substrate to form the structure described herein, the structure includes an additional distance between the passive element and the semiconductor substrate as compared to the case in which the passive element is formed within the IC. This increased distance may significantly reduce interaction between the electromagnetic field of the passive element and the semiconductor substrate material, thereby reducing energy losses due to conduction in the substrate. The insulating materials (which may include, e.g., ceramics or polyimides) surrounding the passive element within the grid-array substrate are typically much lower-loss than the semiconductor substrate and insulating materials (such as silicon dioxide) used in the IC, further contributing to formation of high-Q passive elements.
The passive circuit elements contemplated herein may be formed by patterning one or more conductive layers within the grid-array substrate, using methods similar to those employed in IC fabrication (though the patterns in the grid-array substrate are generally formed to a larger scale). The circuit elements may therefore be formed predictably and reproducibly to provide precise component values.
In an embodiment of a method described herein, a passive circuit element is formed at least in part within a conductive layer of a grid-array substrate. The conductive layer is preferably formed to have a thickness greater than about 5 microns, and may be formed from copper or other conductive materials. Passive circuit elements which may be formed include inductors, capacitors, and transmission lines. Spiral inductors and some types of transmission line, for example, may be patterned within a single conductive layer, while other elements such as capacitors and transmission lines utilizing a ground plane may be formed using two conductive layers separated by an insulating layer. The passive element formation includes patterning of a conductive layer within the grid-array substrate. This conductive layer may be an outermost layer of the grid-array substrate, such that at least a portion of the passive element is formed on a surface of the grid-array substrate. Alternatively, the conductive layer may be covered with an insulating layer after patterning, such that the passive element is formed in the interior of the grid-array substrate. In embodiments for which one or more of the terminals of the passive element are covered by an insulating layer, conductive vias may be subsequently formed to connect the buried terminals to the IC-mounting surface of the grid-array substrate.
A pair of contact pads within the processed surface of a semiconductor-based integrated circuit may be coupled to the terminals of the passive circuit element, preferably by orienting the integrated circuit such that the processed surface faces the IC-mounting surface of the grid-array substrate. Coupling the pair of contact pads to the passive element terminals may include positioning a solder ball or bump, similar to that which may be used on a BGA package, between each pad and the corresponding terminal. Coupling of the contact pads to the passive element terminals, in combination with coupling of additional IC contact pads to corresponding pads on the grid-array substrate, may also constitute mounting of the IC to the grid-array substrate, or vice versa. The grid-array substrate is preferably of larger area than the IC, so that the grid-array substrate may be used for packaging of the IC as well as for formation of the passive circuit element. In some embodiments, however, a grid-array substrate having a smaller area than that of the IC (or area comparable to that of the IC) and including a passive circuit element may be mounted onto the IC. In such an embodiment, the grid-array substrate would be used to provide the passive circuit element, but not to package the IC. Such an IC/passive element arrangement could be packaged using various structures including an additional, larger grid-array substrate.
In some embodiments of the method, the pair of contact pads within the IC is coupled to the terminals of the passive circuit element such that the processed surface of the IC overlaps the portion of the IC-mounting surface of the grid-array substrate which contains the passive circuit element. For example, if the grid-array substrate is configured such that its IC-mounting surface faces upward, the IC in such an embodiment is mounted so as to cover the passive circuit element. In an alternative embodiment, the pair of contact pads is coupled to the terminals of the passive element such that the IC is laterally displaced (in a direction parallel to the surface of the grid-array substrate) from the passive circuit element. In such an embodiment, coupling the pair of contact pads within the IC to the terminals of the passive element may include connecting the pair of IC contact pads to a corresponding pair of contact pads on the grid-array substrate, wherein the contact pads on the grid-array substrate are connected to the terminals of the passive element by interconnect lines within the grid-array substrate. Lateral displacement of the IC from the passive element may be advantageous by further reducing interaction between an electromagnetic field produced by the passive element and the substrate of the integrated circuit.
In some embodiments for which the IC is laterally displaced from the passive element, a low-loss substrate may also be coupled to the IC-mounting surface of the grid-array substrate, such that the low-loss substrate overlaps the portion of the grid-array substrate containing the passive element. The low-loss substrate may be made from materials including alumina and other ceramic materials. Connecting a low-loss substrate to the grid-array substrate in the vicinity of the passive element may be advantageous in providing a low-loss medium proximate to the passive element so that any energy loss associated with the element""s electromagnetic field may be readily predicted. The presence of the low-loss substrate may, for example, reduce interaction of the passive element""s electromagnetic field with other parts of the circuit structure, such as a cover of the grid-array package. Furthermore, coupling of a low-loss substrate to the grid-array package may also allow integration of circuit elements, such as transmission lines, formed directly on the low-loss substrate to be coupled to the IC using interconnect lines within the grid-array substrate.
In addition to the method discussed above, a circuit structure is contemplated herein. The circuit structure includes a passive circuit element formed within a grid-array substrate, and a semiconductor-based IC having a pair of contact pads coupled to a pair of terminals of the passive circuit element. The passive circuit element is formed at least in part within a conductive layer within the grid-array substrate, and may in some embodiments be formed using two or more conductive layers and intervening insulating layers. The passive circuit element, such as an inductor, a capacitor, or a transmission line, may be at least in part on the IC-mounting surface of the grid-array substrate. Alternatively, an insulating layer may separate the passive circuit element from the IC-mounting surface. Each conductive layer from which at least a portion of a passive circuit element is formed preferably has a thickness of at least approximately five microns. More preferably, the conductive layer thickness is more than about fourteen microns. The conductive layer may include copper and/or other conductive materials.
The semiconductor-based IC, typically a silicon-based IC, is preferably oriented so that a processed surface of the IC containing the pair of contact pads is facing the IC-mounting surface of the grid-array substrate. In a preferred embodiment, the grid-array substrate has an area greater than that of the IC, and the grid-array substrate is used for packaging of the IC as well as for providing the passive circuit element. In such an embodiment, additional contact pads of the IC may be coupled to corresponding pads on the grid-array substrate, in addition to the coupling of the pair of contact pads to the terminals of the passive element. Alternatively, the grid-array substrate may have an area comparable to or smaller than that of the IC, and not be used to package the IC. In such an embodiment, the coupling between the terminals of the passive element and the pair of contact pads on the IC may constitute a mounting of the grid-array substrate onto the surface of the IC. The IC/passive element combination may be mounted onto an additional, larger grid-array substrate for packaging. In any of the above embodiments of the circuit structure, the connection formed between one of the pair of contact pads and the corresponding terminal of the passive element may contain a solder ball or bump similar to those used in BGA packages.
In an embodiment of the circuit structure, the lateral extent (in a direction parallel to the surface of the grid-array substrate) of the IC overlaps the lateral extent of the passive circuit element. In an alternative embodiment, the IC is laterally displaced from the passive circuit element, and the coupling between one of the pair of contacts and the corresponding terminal of the passive element may include an interconnect line within the grid-array substrate. In such an embodiment for which the IC is laterally displaced from the passive circuit element, a low-loss substrate may be mounted on the grid-array substrate in addition to the IC, such that the lateral extent of the low-loss substrate overlaps that of the passive circuit element. The low-loss substrate may be formed from a ceramic material, such as alumina, and additional circuit elements may be formed on the low-loss substrate.